View UDA1338H_346558.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
UDA1338H Multichannel audio coder-decoder
Preliminary specification Supersedes data of 2002 May 23 2002 Nov 21
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 9 9.1 9.2 9.3 9.4 9.5 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 FEATURES General Multiple format data interface Digital sound processing Advanced audio configuration APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System clock Audio analog-to-digital converter (audio ADC) Voice analog-to-digital converter (voice ADC) Decimation filter of audio ADC Decimation filter of voice ADC Interpolation filter of DAC Noise shaper of DAC Digital mixer Audio digital-to-analog converters Power-on reset Audio digital interface Voice digital interface DSD mode Microcontroller interface mode L3-BUS INTERFACE General Device addressing Register addressing Data write mode Data read mode I2C-BUS INTERFACE General Characteristics of the I2C-bus Bit transfer Byte transfer Data transfer Start and stop conditions Acknowledgment Device address Register address Write and read data Write cycle Read cycle 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 12 13 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 20.5 21 22 23 24 REGISTER MAPPING
UDA1338H
Address mapping Register mapping System settings Audio ADC and DAC subsystem settings Voice ADC system settings Status output register (read only) DAC channel selection DAC features settings DAC channel 1 to 6 settings DAC mixing channel settings Audio ADC 1 and ADC 2 input amplifier gain settings Voice ADC gain settings Supplemental settings 1 Supplemental settings 2 LIMITING VALUES HANDLING QUALITY SPECIFICATION THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS TIMING PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2002 Nov 21
2
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
1 1.1 FEATURES General
UDA1338H
* 2.7 to 3.6 V power supply * 5 V tolerant digital inputs * 24-bit data path * Selectable control: via L3-bus or I2C-bus microcontroller interface * Supports sample frequency ranges for: - Audio ADC: fs = 16 to 100 kHz - Voice ADC: fs = 7 to 50 kHz - Audio DAC: fs = 16 to 200 kHz. * Separate power control for ADC and DAC * ADC plus integrated high-pass filter to cancel DC offset * Integrated digital filter plus DAC * Slave mode only applications * Easy application. 1.2 Multiple format data interface 2 APPLICATIONS * Excellently suitable for multichannel home audio-video application. 3 GENERAL DESCRIPTION * Outputs: - 6 differential audio outputs (3 x stereo) * DSD mode to support stereo DSD playback * High linearity, wide dynamic range and low distortion * DAC digital filter with selectable sharp or soft roll-off.
* Audio interface supports standard I2S-bus, MSB-justified, LSB-justified and two multichannel formats * Voice interface supports I2S-bus and mono channel formats. 1.3 Digital sound processing
The UDA1338H is a single-chip consisting of 4 plus 1 analog-to-digital converters and 6 digital-to-analog converters with signal processing features employing bitstream conversion techniques. The multichannel configuration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature. The UDA1338H supports conventional 2 channels per line data transfer conformable to the I2S-bus format with word lengths of up to 24 bits, the MSB-justified format with word lengths of up to 24 bits and the LSB-justified format with word lengths of 16, 20 and 24 bits, as well as 4 to 6 channels per line transfer mode. The device also supports a combination of the MSB-justified output format and the LSB-justified input format. The UDA1338H has special sound processing features in the Direct Stream Digital (DSD) playback mode, de-emphasis, volume and mute which can be controlled via the L3-bus or I2C-bus interface.
* Control via L3-bus or I2C-bus: - Channel independent digital logarithmic volume - Digital de-emphasis for fs = 32, 44.1, 48 or 96 kHz - Soft or quick mute - Output signal polarity control. 1.4 Advanced audio configuration
* Inputs: - 4 single-ended audio inputs (2 x stereo) with programmable gain amplifiers - 1 single-ended voice input 4 ORDERING INFORMATION TYPE NUMBER UDA1338H
PACKAGE NAME QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm VERSION SOT307-2
2002 Nov 21
3
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
5 QUICK REFERENCE DATA VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 C; RL = 22 k; all voltages referenced to ground (pins VSS); unless otherwise specified. SYMBOL Supplies VDDA(AD) VDDA(DA) VDDD IDDA(AD) IDDA(DA) IDDD IDDD(pd) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current digital supply current digital supply current in Power-down mode ambient temperature fADC = 48 kHz fDAC = 48 kHz fADC = fDAC = 48 kHz; fVOICE = 48 kHz audio and voice ADCs power-down DAC power-down Tamb D0 (THD+N)/S S/N cs Audio analog-to-digital converter digital output level at 0 dB setting; 900 mV -2.5 (RMS) input; notes 1 and 2 - - 94 - -1.2 -90 -40 100 100 -0.7 -83 -34 - - dB dB dB dB dB 2.7 2.7 2.7 - - - - - -20 3.3 3.3 3.3 30 20 31 tbf tbf - 3.6 3.6 3.6 - - - - - +85 V V V mA mA mA mA mA C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
total harmonic distortion-plus-noise at -1 dBFS to signal ratio at -60 dBFS; A-weighted signal-to-noise ratio channel separation code = 0; A-weighted
Digital-to-analog converter DIFFERENTIAL MODE Vo(rms) (THD+N)/S S/N cs Vo(rms) (THD+N)/S S/N cs Notes 1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. output voltage (RMS value) at 0 dBFS digital input 1.9 - - 107 - at 0 dBFS digital input - - - - - 2.0 -100 -50 114 117 2.1 -93 -45 - - - - - - - V dB dB dB dB total harmonic distortion-plus-noise at 0 dBFS to signal ratio at -60 dBFS; A-weighted signal-to-noise ratio channel separation code = 0; A-weighted
SINGLE-ENDED MODE output voltage (RMS value) 1.0 -90 -45 110 114 V dB dB dB dB total harmonic distortion-plus-noise at 0 dBFS to signal ratio at -60 dBFS; A-weighted signal-to-noise ratio channel separation code = 0; A-weighted
2002 Nov 21
4
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
6 BLOCK DIAGRAM
UDA1338H
handbook, full pagewidth
VDDA(AD) 5 VINL1 2 PGA ADC 1L
VSSA(AD) 3
VADCP 9 ADC 1R
VADCN 7 PGA
Vref 1 4 VINR1
VINL2
6 PGA 10 LNA
ADC 2L
ADC 2R
PGA
8
VINR2
VVOICE
DECIMATION FILTER ADC DC-CANCELLATION FILTER
TEST
11
TEST
DECIMATION FILTER HP FILTER DATAV BCKV WSV PLL 21 MCCLK MCMODE MCDATA I2C_L3 20 22 30 L3-BUS OR I2C-BUS CONTROL INTERFACE 16 17 18 I2S-BUS INTERFACE 3
CLOCK
19
SYSCLK
I2S-BUS INTERFACE 1
13 12 14 15
DATAAD1 DATAAD2 BCKAD WSAD
PLL 23 I2S-BUS INTERFACE 2 24 25 26 27 WSDA BCKDA DATADA1 DATADA2 DATADA3
VOLUME, MUTE, DE-EMPHASIS 29 28 NOISE SHAPER VDDD VSSD
INTERPOLATION FILTER
UDA1338H
VOUT1N VOUT1P VOUT3N VOUT3P VOUT5N VOUT5P
32 31 36 35 42 41
- + - + - + 37 VDDA(DA) DAC 5 40 DAC 6 DAC 3 DAC 4 DAC 1 DAC 2
- + - + - +
34 33 39 38 44 43
VOUT2N VOUT2P VOUT4N VOUT4P VOUT6N VOUT6P
MGU581
VSSA(DA)
Fig.1 Block diagram.
2002 Nov 21
5
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
7 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 TYPE(1) AIO AIO AGND AIO AS AIO AIO AIO AIO AIO DID DESCRIPTION ADC reference voltage ADC 1 input left ADC analog ground ADC 1 input right ADC analog supply voltage ADC 2 input left ADC reference voltage N ADC 2 input right ADC reference voltage P voice ADC input test input; must be connected to digital ground (VSSD) in application ADC 2 data output ADC 1 data output ADC bit clock input ADC word select input voice data output voice bit clock input voice word select input or output system clock input: 256fs, 384fs, 512fs or 768fs L3-bus L3MODE input or I2C-bus DAC mute control input L3-bus L3CLOCK input or I2C-bus SCL input L3-bus L3DATA input and output or I2C-bus SDA input and output DAC word select input DAC bit clock input DAC channel 1 and channel 2 data input DAC channel 3 and channel 4 data input DAC channel 5 and channel 6 data input digital ground VOUT4P VOUT4N VSSA(DA) VOUT5P VOUT5N VOUT6P VOUT6N Note 1. See Table 1. Table 1 TYPE AGND AIO AS DGND DI DID DIO DIS DO DS IIC Pin types 38 39 40 41 42 43 44 AIO AIO AGND AIO AIO AIO AIO VOUT1P VOUT1N VOUT2P VOUT2N VOUT3P VOUT3N VDDA(DA) 31 32 33 34 35 36 37 AIO AIO AIO AIO AIO AIO AS
UDA1338H
SYMBOL VDDD I2C_L3
PIN 29 30
TYPE(1) DS DI
DESCRIPTION digital supply voltage selection input for L3-bus or I2C-bus control DAC 1 positive output DAC 1 negative output DAC 2 positive output DAC 2 negative output DAC 3 positive output DAC 3 negative output DAC analog supply voltage DAC 4 positive output DAC 4 negative output DAC analog ground DAC 5 positive output DAC 5 negative output DAC 6 positive output DAC 6 negative output
SYMBOL Vref VINL1 VSSA(AD) VINR1 VDDA(AD) VINL2 VADCN VINR2 VADCP VVOICE TEST
DATAAD2 DATAAD1 BCKAD WSAD DATAV BCKV WSV SYSCLK MCMODE
12 13 14 15 16 17 18 19 20
DO DO DIS DI DO DIS DIO DIS DI
DESCRIPTION analog ground analog input and output analog supply digital ground digital input digital input with internal pull-down resistor digital input and output digital Schmitt-triggered input digital output digital supply input and open-drain output for I2C-bus
MCCLK MCDATA
21 22
DIS IIC
WSDA BCKDA DATADA1 DATADA2 DATADA3 VSSD
23 24 25 26 27 28
DI DIS DI DI DI DGND
2002 Nov 21
6
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
37 VDDA(DA)
40 VSSA(DA)
44 VOUT6N
42 VOUT5N
39 VOUT4N
36 VOUT3N
handbook, full pagewidth
Vref VINL1 VSSA(AD) VINR1 VDDA(AD) VINL2 VADCN VINR2 VADCP
1 2 3 4 5 6 7 8 9
34 VOUT2N
43 VOUT6P
41 VOUT5P
38 VOUT4P
35 VOUT3P
33 VOUT2P 32 VOUT1N 31 VOUT1P 30 I2C_L3 29 VDDD
UDA1338H
28 VSSD 27 DATADA3 26 DATADA2 25 DATADA1 24 BCKDA 23 WSDA
VVOICE 10 TEST 11
DATAAD2 12
DATAAD1 13
BCKAD 14
WSAD 15
DATAV 16
BCKV 17
WSV 18
SYSCLK 19
MCMODE 20
MCCLK 21
MCDATA 22
MGU583
Fig.2 Pin configuration.
2002 Nov 21
7
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
8 8.1 FUNCTIONAL DESCRIPTION System clock
UDA1338H
The mode of operation of the audio and voice channels can be set via the L3-bus or I2C-bus microcontroller interface and are summarized in Tables 2 and 3. When applied, the system clock must be locked in frequency to the corresponding digital interface clocks. The voice ADC part can either receive or generate the WSV signal as shown in Table 3.
The UDA1338H operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock. The audio ADC part, the voice ADC part and the DAC part can operate at different sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency (SYSCLK, WSDA and DSD modes). The voice ADC part supports a sampling frequency up to 50 kHz and the audio ADC supports a sampling frequency up to 100 kHz. The DAC sampling frequency range is extended up to 200 kHz with the range above 100 kHz being supported through 192 kHz sampling mode, which halves the oversampling ratio of SYSCLK and internal clocks. Table 2 Audio ADC and DAC operating clock mode AUDIO ADC MODE CLOCK SYSCLK SYSCLK
AUDIO DAC CLOCK SYSCLK SYSCLK FREQUENCY 256fs, 384fs, 512fs or 768fs 128fs, 192fs, 256fs or 384fs; 192 kHz sampling mode 1fs 256fs, 384fs, 512fs or 768fs 128fs, 192fs, 256fs or 384fs; 192 kHz sampling mode 1fs 44.1 kHz x 512
FREQUENCY 256fs, 384fs, 512fs or 768fs
DAC-WS ADC-WS
SYSCLK WSAD
256fs, 384fs, 512fs or 768fs 1fs
WSDA SYSCLK SYSCLK
WSDA DSD Table 3
WSDA SYSCLK
1fs 44.1 kHz x 512
WSDA SYSCLK
Voice ADC operating clock mode VOICE ADC
MODE BIT CLOCK FREQUENCY (BCKV) WSV-in WSV-out input: 32fs, 64fs, 128fs or 256fs input: 32fs, 64fs, 128fs or 256fs input output WORD SELECT (WSV)
2002 Nov 21
8
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
8.2 Audio analog-to-digital converter (audio ADC) 8.5
UDA1338H
Decimation filter of voice ADC
The audio analog-to-digital front-end of the UDA1338H consists of 4-channel single-ended Adds with programmable gain stage (from 0 to 24 dB with 3 dB steps), controlled via the microcontroller interface. Using the PGA feature, it is possible to accept an input signal of 900 mV (RMS) or 1.8 V (RMS) if an external resistor of 10 k is used in series. The schematic of audio ADC front-end is shown in Fig.3.
The voice ADC decimation filter is realized with the combination of a Finite Impulse Response (FIR) filter and Infinite Impulse Response (IIR) filter for shorter group delay. The filter characteristics are shown in Table 5. During the power-on sequence, the output of the ADC is hard muted for a certain period. This hard-mute time can be chosen between 1024 and 2048 samples. Table 5 Decimation filter characteristics (voice ADC) CONDITION 0 to 0.45fs 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.05 -0.2 -65 >110
ITEM
handbook, halfpage
Pass-band ripple
10 k (0 dB setting)
Pass-band droop Stop band
ADC
input signal 2 V (RMS)
VINL, 10 k VINR
10 k
Dynamic range 8.6
Vref
VDDA = 3.3 V
MGU582
Interpolation filter of DAC
Fig.3 Schematic of audio ADC front-end.
The digital interpolation filter interpolates from 1fs to 128fs (or to 64fs in the 192 kHz sampling mode) by cascading FIR filters, and has two sets of filter coefficients for sharp and slow roll-off as given in Tables 6 and 7. Table 6 Interpolation filter characteristics (sharp roll-off) CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.002 -75 >135
8.3
Voice analog-to-digital converter (voice ADC)
The voice analog-to-digital front-end of the UDA1338H consists of a single-channel single-ended ADC with a fixed gain (26 dB) Low Noise Amplifier (LNA). Together with the digital variable gain amplification stage, the voice ADC provides optimal processing and reproduction of the microphone signal. The supported sampling frequency range is from 7 to 50 kHz. Power-down of the LNA and the ADC can be controlled separately. 8.4 Decimation filter of audio ADC
4
ITEM Pass-band ripple Stop band Dynamic range Table 7
Interpolation filter characteristics (slow roll-off) CONDITION 0 to 0.22fs 0.45fs >0.78fs 0 to 0.22fs VALUE (dB) 0.002 -3.1 -94 >135
ITEM Pass-band ripple Pass-band droop Stop band Dynamic range 8.7
The decimation from 64fs is performed in two stages. sin x The first stage realizes ---------- x - characteristics with a
decimation factor of 8. The second stage consists of three half-band filters, each decimating by a factor of 2. The filter characteristics are shown in Table 4. Table 4 Decimation filter characteristics (audio ADC) CONDITION 0 to 0.45fs 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.01 -0.2 -70 >135 9
Noise shaper of DAC
ITEM Pass-band ripple Pass-band droop Stop band Dynamic range 2002 Nov 21
The 3rd-order noise shaper operates at either 128fs or 64fs (in the 192 kHz sampling mode), and converts the 24-bit input signal into a 5-bit signal stream. The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved.
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
8.8 Digital mixer
UDA1338H
The UDA1338H has 6 digital mixers inside the interpolator (see Fig.4). The ADC signals can be mixed with the I2S-bus input signals. The mixing of the ADC signals can be selected by the bits MIX[1:0].
MIX [1:0 handbook, full pagewidth ] from ADC ch1 ch2 ch3 ch4 DE-EMPHASIS from I 2S-bus VOLUME MUTE 1fs mixer input MIXER VOLUME MIXER MUTE
+
INTERPOLATION FILTER
DAC1
DATADA1 same as above DAC2
same as above DATADA2 same as above
DAC3
DAC4
same as above DATADA3
DAC5
same as above DIS [1:0]
MGW786
DAC6
ICS [1:0]
Fig.4 Block diagram of DAC mixer.
8.9
Audio digital-to-analog converters
The audio digital-to-analog front-end of the UDA1338H consists of 6-channel differential SDACs: an SDAC is a multi-bit DAC based upon switched resistors. To minimize data dependent modulation effects, a Dynamic Element Matching (DEM) algorithm scrambler circuit and DC current compensation circuit are implemented with the SDAC. 8.10 Power-on reset
The reset time (see Fig.6) is determined by an external capacitor which is connected between pin Vref and ground. The reset time should be at least 250 s for Vref < 1.25 V. When VDDA(AD) is switched off, the device will be reset again for Vref < 0.75 V. During the reset time, the system clock should be running.
The UDA1338H has an internal power-on reset circuit which initializes the device (see Fig.5). All the digital sound processing features and the system controlling features are set to their default values in the L3-bus and the I2C-bus modes. 2002 Nov 21 10
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
8.11 Audio digital interface
UDA1338H
handbook, halfpage
VDDA(AD) 9 k Vref C1 > 10 F 9 k
MGU585
The following audio formats can be selected via the microcontroller interface: * I2S-bus format with data word length of up to 24 bits
RESET CIRCUIT
* MSB-justified format with data word length of up to 24 bits * LSB-justified format with data word length of 16, 20 or 24 bits * Multichannel formats with data word length of 20 or 24 bits. The used data lines are DATAAD1 and DATADA1 and the sampling frequency must be below 50 kHz. The formats are illustrated in Figs 7 and 8. 8.12 Voice digital interface
Fig.5 Power-on reset circuit.
The following voice formats can be selected via the microcontroller interface:
3.3
handbook, halfpage
VDDD (V)
* I2S-bus format with data word length of up to 20 bits. The left and the right channels contain the same data. * Mono channel format with data word length of up to 20 bits.
0 t 3.3 VDDA(AD) (V)
The formats are illustrated in Fig.9.
0
t
Vref (V) 1.65 1.25 0.75 0 >250 s trst t
MGU586
Fig.6 Power-on reset timing.
2002 Nov 21
11
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
andbook, full pagewidth
2002 Nov 21 2002 Nov 21 12 12
Philips Semiconductors
Multichannel audio coder-decoder Multichannel audio coder-decoder
WS 1 BCK 2 3
LEFT >=8 1 2 3
RIGHT
>=8
DATA
MSB
B2
MSB
B2
MSB
I2S-BUS FORMAT
WS 1 BCK 2
LEFT 3 >=8 1 2
RIGHT 3 >=8
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MSB-JUSTIFIED FORMAT
WS
LEFT 16 15 2 1
RIGHT 16 15 2 1
BCK
DATA
MSB
B2
B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
MSB
B2
B15 LSB
WS
LEFT 20 19 18 17 16 15 2 1
RIGHT 20 19 18 17 16 15 2 1
BCK
DATA
MSB
B2
B3
B4
B5
B6
B19 LSB LSB-JUSTIFIED FORMAT 20 BITS
MSB
B2
B3
B4
B5
B6
B19 LSB
WS 24 BCK 23 22 21
LEFT 20 19 18 17 16 15 2 1 24 23 22 21
RIGHT 20 19 18 17 16 15 2 1
Preliminary specification
DATA
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB LSB-JUSTIFIED FORMAT 24 BITS
MSB
B2
B3
B4
B5
B6
B7
B8
B9
B10
B23 LSB
MGT020
UDA1338H UDA1338H
Fig.7 Formats of input and output data (single-channel).
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
k, full pagewidth
2002 Nov 21 2002 Nov 21
WS 1 BCK 2 21 22 41 42 61 DATA MSB CH1 LSB MSB CH3 LSB MSB CH5 LSB WS 1 BCK 2 25 26 49 50 73 DATA MSB CH1 LSB MSB CH3 LSB MSB CH5 LSB
Philips Semiconductors
Multichannel audio coder-decoder Multichannel audio coder-decoder
1
2
21
22
41
42
61
MSB CH2
LSB
MSB CH4
LSB
MSB CH6
LSB
MULTICHANNEL FORMAT 20 BITS
1
2
25
26
49
50
73
MSB CH2
LSB
MSB CH4
LSB
MSB CH6
LSB
13 13
WS 1 BCK DATA
MULTICHANNEL FORMAT 24 BITS (1)
25
26
49
50
73
74
97
1
25
26
49
50
73
74
97
MSB CH1
LSB MSB CH3
LSB MSB CH5
LSB
MSB CH2
LSB MSB CH4
LSB MSB CH6
LSB
MULTICHANNEL FORMAT 24 BITS (2)
MGU588
Preliminary specification
UDA1338H UDA1338H
(1) Format 1. (2) Format 2.
Fig.8 Formats of input and output data (multichannel).
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
handbook, full pagewidth WS
LEFT 1 2 3 8 1 2 3
RIGHT 8
BCK
DATA
MSB
B2
MSB I2S-BUS FORMAT
B2
MSB
WS 1 BCK 2 3 8 1 2
DATA
MSB
B2 MONO CHANNEL FORMAT
MSB
B2
MGU587
Fig.9 Voice digital interface formats.
8.13
DSD mode
The UDA1338H can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The configuration of the UDA1338H in the DSD mode is shown in Fig.10.
left channel 2.8224 MHz DSD right channel
DATADA2 DECIMATION FILTER DATADA3 INTERPOLATION NOISE SHAPING
DAC
- + - +
VOUT1N VOUT1P VOUT2N VOUT2P right channel left channel analog output
DAC
5.6448 MHz 88.2 kHz
BCKAD WSAD I2S-BUS INTERFACE 1 I2S-BUS INTERFACE 2
MGU584
DATAAD1
DATADA1 88.2 kHz PCM data
WSDA BCKDA
SYSCLK
I2S-bus (left and right)
88.2 kHz 22.5792 MHz 5.6448 MHz
Fig.10 DSD mode
2002 Nov 21
14
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
8.14 Microcontroller interface mode
UDA1338H
The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by signal L3MODE = LOW and a burst of 8 pulses for signal L3CLOCK, accompanied by 8 bits (see Fig.11). The data transfer mode is characterized by signal L3MODE = HIGH and is used to transfer one or more bytes representing a register address, instruction or data. Basically, two types of data transfers can be defined: * Write action: data transfer to the device * Read action: data transfer from the device. 9.2 Device addressing
The microcontroller interface mode can be selected as shown in Table 8: * L3-bus mode when pin I2C_L3 = LOW * I2C-bus mode when pin I2C_L3 = HIGH. Table 8 Pin function in the L3-bus or I2C-bus mode LEVEL ON PIN I2C_L3 PIN LOW L3-BUS MODE SIGNAL MCCLK MCDATA MCMODE Table 9 QMUTE FUNCTION L3CLOCK L3DATA L3MODE HIGH I2C-BUS MODE SIGNAL SCL SDA QMUTE
The device address consists of one byte with: * Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 8) * Address bits 2 to 7 representing a 6-bit device address. The address of the UDA1338H is 01 0100 (bits 2 to 7). Table 10 Selection of data transfer
SIGNAL QMUTE LOW HIGH no muting muting
DOM TRANSFER BIT 0 BIT 1 0 0 1 1 not used not used write data or prepare read read data 0 1 0 1 9.3
All the features are accessible with the I2C-bus interface protocol as with the L3-bus interface protocol. The detailed description of the device operation in the L3-bus mode and I2C-bus mode is given in Chapters 9 and 10, respectively. 9 9.1 L3-BUS INTERFACE General
Register addressing
The UDA1338H has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The exchange of data and control information between the microcontroller and the UDA1338H is LSB first and is accomplished through a serial hardware L3-bus interface comprising the following pins: * MCCLK: clock line with signal L3CLOCK * MCDATA: data line with signal L3DATA * MCMODE: mode line with signal L3MODE. The L3-bus format has two modes of operation: * Address mode * Data transfer mode.
After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. Basically, there are 3 methods for register addressing: 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.11) 2. Addressing for prepare read: bit is logic 1, indicating that data will be read from the register (see Fig.12) 3. Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid (see Fig.12).
2002 Nov 21
15
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Nov 21 2002 Nov 21
L3CLOCK L3MODE device address L3DATA 0 1 0
MBL567
Philips Semiconductors
Multichannel audio coder-decoder Multichannel audio coder-decoder
register address
data byte 1
data byte 2
DOM bits
write
Fig.11 Data write mode. 16 16
L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 register address data byte 1 data byte 2
Preliminary specification
valid/invalid
UDA1338H UDA1338H
send by the device
MBL565
Fig.12 Data read mode.
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
9.4 Data write mode
UDA1338H
For reading data from a device, the following 6 bytes are involved (see Table 12): 1. Byte 1 with the device address, including `01' for signalling the write action to the device. 2. Byte 2 is sent with the register address from which data needs to be read. This byte starts with a `1', which indicates that there will be a read action from the register, followed by 7 bits for the destination address in binary format, with bit A6 being the MSB and bit A0 being the LSB. 3. Byte 3 with the device address, including `11' is sent to the device. The `11' indicates that the device must write data to the microcontroller. 4. Byte 4 sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1). 5. Byte 5 sent by the device to the bus, with the data information in binary format, with bit D15 being the MSB. 6. Byte 6 sent by the device to the bus, with the data information in binary format, with bit D0 being the LSB.
The data write mode is explained in the signal diagram of Fig.11. For writing data to a device, 4 bytes must be sent (see Table 11): 1. Byte 1 starting with `01' for signalling the write action to the device, followed by the device address `01 0100'. 2. Byte 2 starting with a `0' for signalling the write action, followed by 7 bits indicating the destination address in binary format with bit A6 being the MSB and bit A0 being the LSB. 3. Byte 3 with bit D15 being the MSB. 4. Byte 4 with bit D0 being the LSB. It should be noted that each time a new destination register address needs to be written, the device address must be sent again. 9.5 Data read mode
To read data from the device, a prepare read must first be done and then data read. The data read mode is explained in the signal diagram of Fig.12.
Table 11 L3-bus write data BYTE 1 2 3 4 L3-BUS MODE address data transfer data transfer data transfer FIRST IN TIME ACTION BIT 0 device address register address data byte 1 data byte 2 0 0 D15 D7 BIT 1 1 A6 D14 D6 BIT 2 0 A5 D13 D5 BIT 3 1 A4 D12 D4 BIT 4 0 A3 D11 D3 BIT 5 1 A2 D10 D2 BIT 6 0 A1 D9 D1 BIT 7 0 A0 D8 D0 LATEST IN TIME
Table 12 L3-bus read data BYTE 1 2 3 4 5 6 L3-BUS MODE address data transfer address data transfer data transfer data transfer FIRST IN TIME ACTION BIT 0 device address register address device address register address data byte 1 data byte 2 0 1 1 0 or 1 D15 D7 BIT 1 1 A6 1 A6 D14 D6 BIT 2 0 A5 0 A5 D13 D5 BIT 3 1 A4 1 A4 D12 D4 BIT 4 0 A3 0 A3 D11 D3 BIT 5 1 A2 1 A2 D10 D2 BIT 6 0 A1 0 A1 D9 D1 BIT 7 0 A0 0 A0 D8 D0 LATEST IN TIME
2002 Nov 21
17
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
10 I2C-BUS INTERFACE 10.1 General 10.3 Bit transfer
UDA1338H
The UDA1338H has an I2C-bus microcontroller interface. All the features are accessible with the I2C-bus interface protocol. In the I2C-bus mode, the DAC mute function is accessible via pin MCMODE with signal QMUTE. The exchange of data and control information between the microcontroller and the UDA1338H is accomplished through a serial hardware interface comprising the following pins as shown in Table 8: * MCCLK: clock line with signal SCL * MCDATA: data line with signal SDA. 10.2 Characteristics of the I2C-bus
One data bit is transferred during each clock pulse (see Fig.13). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run on this high frequency, all the inputs and outputs connected to this bus must be designed for this high-speed I2C-bus according to the Philips specification. 10.4 Byte transfer
Each byte (8 bits) is transferred with the MSB first (see Table 13). Table 13 Byte transfer MSB 7 10.5 6 5 BIT NUMBER 4 3 2 1 LSB 0
The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the supply voltage VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC, the recommendation for this type of bus from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 and 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy.
Data transfer
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.13 Bit transfer on the I2C-bus.
2002 Nov 21
18
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
10.6 Start and stop conditions
UDA1338H
A slave receiver which is addressed, must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S); see Fig.14. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P). 10.7 Acknowledgment
The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.15). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse.
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.14 START and STOP conditions on the I2C-bus.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.15 Acknowledge on the I2C-bus.
2002 Nov 21
19
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
10.8 Device address I2C-bus, 10.9 Register address
UDA1338H
the device Before any data is transmitted on the which should respond is addressed first. The addressing is always done with byte 1 transmitted after the start procedure. The UDA1338H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1338H device address is shown in Table 14. Table 14 I2C-bus device address of UDA1338H DEVICE ADDRESS A6 0 A5 0 A4 1 A3 1 A2 0 A1 0 A0 0 R/W - 0/1
The register addresses in the I2C-bus mode are the same as in the L3-bus mode. The register addresses are defined in Chapter 11. 10.10 Write and read data The I2C-bus configurations for a write and read cycle are shown in Tables 15 and 16, respectively. The write cycle is used to write groups of two bytes to the internal registers for the settings. It is also possible to read the registers for the device status information.
2002 Nov 21
20
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10.11 Write cycle 2002 Nov 21 2002 Nov 21 21 21 S Note 1. Auto increment of register address. Philips Semiconductors
Multichannel audio coder-decoder Multichannel audio coder-decoder
The I2C-bus configuration for a write cycle is shown in Table 15. The write cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a pair of two bytes. The format of the write cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `0011 000' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1338H. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1338H must start. 5. The UDA1338H acknowledges this register address (A). 6. The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the UDA1338H. 7. If repeated groups of 2 bytes data are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the UDA1338H. 8. Finally, the UDA1338H frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 15 Master transmitter writes to UDA1338H registers in the I2C-bus mode DEVICE ADDRESS 0011 000 R/W 0 A REGISTER ADDRESS ADDR A MS1 DATA 1 A LS1 A MS2 DATA 2(1) A LS2 A MSn DATA n(1) A LSn A P
acknowledge from UDA1338H
Preliminary specification
UDA1338H UDA1338H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10.12 Read cycle 2002 Nov 21 2002 Nov 21 22 22 Philips Semiconductors
Multichannel audio coder-decoder Multichannel audio coder-decoder
The read cycle is used to read the data values from the internal registers. The I2C-bus configuration for a read cycle is shown in Table 16. The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `0011 000' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1338H. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the reading of the register content of the UDA1338H must start. 5. The UDA1338H acknowledges this register address. 6. Then the microcontroller generates a repeated start (Sr). 7. Then the microcontroller generates the device address `0011 000' again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1338H. 8. The UDA1338H sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller (master). 9. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the microcontroller. 10. The microcontroller stops this cycle by generating a negative acknowledge (NA). 11. Finally, the UDA1338H frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 16 Master transmitter reads from the UDA1338H registers in the I2C-bus mode DEVICE R/W ADDRESS S 0011 000 0 A REGISTER ADDRESS ADDR A Sr DEVICE R/W ADDRESS 0011 000 1 A MS1 DATA 1 A LS1 A MS2 DATA 2(1) A LS2 A MSn DATA n(1) A LSn NA P
acknowledge from UDA1338H Note 1. Auto increment of register address.
acknowledge from master
Preliminary specification
UDA1338H UDA1338H
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
11 REGISTER MAPPING
UDA1338H
In this chapter the register addressing and mapping of the microcontroller interface of the UDA1338H is given. In Table 17 an overview of the register mapping is given. In Table 18 the actual register mapping is given and the register definitions are explained in Sections 11.3 to 11.14. 11.1 Address mapping
Table 17 Overview of register mapping ADDRESS System settings 00H 01H 02H system audio ADC and DAC subsystem voice ADC system FUNCTION
Status (read out registers) 0FH status outputs
Interpolator settings 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH DAC channel and feature selection DAC feature control DAC channel 1 DAC channel 2 DAC channel 3 DAC channel 4 DAC channel 5 DAC channel 6 DAC mixing channel 1 DAC mixing channel 2 DAC mixing channel 3 DAC mixing channel 4 DAC mixing channel 5 DAC mixing channel 6
ADC input amplifier gain settings 20H 21H audio ADC input amplifier gain voice ADC input amplifier gain
Supplemental settings 30H 31H supplemental settings 1 supplemental settings 2
2002 Nov 21
23
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 11.2 Register mapping 2002 Nov 21 2002 Nov 21 24 24 11H 12H 13H 14H 15H 16H 17H Philips Semiconductors
Multichannel audio coder-decoder Multichannel audio coder-decoder
Table 18 UDA1338H register mapping; note 1 ADD FUNCTION D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
System settings 00H 01H system audio ADC and DAC subsystem voice ADC system RST(2) VFS1 VFS0 - DC 1 - 0 - 0 PAB 0 - 0 - 0 PAA 0 - 0 - VCE 1 MTB 0 - 0 - VAP 0 MTA 0 - 0 - DSD 0 AIF2 0 - 0 - SC1 0 AIF1 0 - 0 - SC0 0 AIF0 0 - 0 - OP1 0 DAG 0 OP0 0 FIL 0 FS1 0 DVD 0 WSM 1 FS0 1 DIS1 0 VH1 0 ACE 1 DIS0 0 VH0 1 ADP 0 DIF2 0 PVA 0 DCE 1 DIF1 0 MTV 0 DAP 0 DIF0 0 VIF 0
02H
BCK1 BCK0 0 - 1 -
Status (read out only) 0FH status outputs VS AS1 AS0 DS2 DS1 DS0
Interpolator settings 10H DAC channel and feature selection DAC feature control DAC channel 1 DAC channel 2 DAC channel 3 DAC channel 4 DAC channel 5 DAC channel 6 MIX1 0 ICS1 0 ICS1 0 - 0 ICS1 0 - 0 ICS1 0 - 0 MIX0 0 ICS0 0 ICS0 0 - 0 ICS0 0 - 0 ICS0 0 - 0 MC5 0 DE2 0 DE2 0 DE2 0 DE2 0 DE2 0 DE2 0 DE2 0 MC4 0 DE1 0 DE1 0 DE1 0 DE1 0 DE1 0 DE1 0 DE1 0 MC3 0 DE0 0 DE0 0 DE0 0 DE0 0 DE0 0 DE0 0 DE0 0 MC2 0 PD 0 PD 0 PD 0 PD 0 PD 0 PD 0 PD 0 MC1 0 MT 0 MT 0 MT 0 MT 0 MT 0 MT 0 MT 0 MC0 0 QM 0 QM 0 QM 0 QM 0 QM 0 QM 0 QM 0 SEL1 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 SEL0 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 CS5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 CS4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 CS3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 CS2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 CS1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 CS0 0 VC0 0 VC0 0 VC0 0 VC0 0 VC0 0
Preliminary specification
UDA1338H UDA1338H
VC0 0 VC0 0
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Nov 21 2002 Nov 21 25 25 21H 30H 31H Note 1. When writing new settings via the L3-bus interface, the default values should always be set to warrant correct operation. Read access to the DAC features register 11H will not return valid data. 2. When bit RST is set to logic 1, the default values are set to all the registers as shown in Table 18. When start-up, all the registers in 00H are initialized as the default values and the mute control bits MTA, MTB, MTV, MT and QM are set to logic 1. All other registers have non fixed values. Philips Semiconductors ADD 18H 19H 1AH 1BH 1CH 1DH FUNCTION DAC mixing channel 1 DAC mixing channel 2 DAC mixing channel 3 DAC mixing channel 4 DAC mixing channel 5 DAC mixing channel 6 D15 ICS1 0 - 0 ICS1 0 - 0 ICS1 0 - 0 - 0 - - D14 ICS0 0 - 0 ICS0 0 - 0 ICS0 0 - 0 - 0 - - D13 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - D12 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - D11 - 0 - 0 - 0 - 0 - 0 - 0 D10 PD 0 PD 0 PD 0 PD 0 PD 0 PD 0 D9 MT 0 MT 0 MT 0 MT 0 MT 0 MT 0 D8 QM 0 QM 0 QM 0 QM 0 QM 0 QM 0 D7 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 VC7 0 - 0 - 0 D6 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 VC6 0 - 0 - 0 D5 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 VC5 0 - 0 - 0 D4 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 VC4 0 - 0 IV4 0 D3 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 VC3 0 D2 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 VC2 0 D1 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 VC1 0 D0 VC0 0 VC0 0 VC0 0 VC0 0 VC0 0 VC0 0
Multichannel audio coder-decoder Multichannel audio coder-decoder
ADC input amplifier gain settings 20H ADC 1 and ADC 2 input amplifier gain voice ADC input amplifier gain IB3 0 - - IB2 0 - - IB1 0 - - IB0 0 - - IA3 0 IV3 0 IA2 0 IV2 0 IA1 0 IV1 0 IA0 0 IV0 0
Supplemental settings supplemental settings 1 supplemental settings 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 PDT 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 VMTP 0 - 0 PDLN A 0 Preliminary specification
DITH2 DITH1 DITH0 0 0 0
UDA1338H UDA1338H
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
11.3 System settings
UDA1338H
Table 19 System register (address 00H) BIT Symbol Reset default BIT Symbol Reset default 15 RST - 7 OP1 0 14 VFS1 0 6 OP0 0 13 VFS0 0 5 FS1 0 12 VCE 1 4 FS0 1 11 VAP 0 3 ACE 1 10 DSD 0 2 ADP 0 9 SC1 0 1 DCE 1 8 SC0 0 0 DAP 0
Table 20 Description of system register bits BIT 15 14 to 13 12 11 SYMBOL RST VFS[1:0] VCE VAP DESCRIPTION Reset. A 1-bit value to initialize the L3-bus registers with the default settings by writing bit RST = 1. If bit RST = 0, there is no reset. Voice ADC sampling frequency. A 2-bit value to select the voice ADC sampling frequency. Default 00. See Table 21. Voice ADC clock enable. A 1-bit value to enable the voice ADC clock. If bit VCE = 1 (default), then the clock is enabled; if bit VCE = 0, then the clock is disabled. Voice ADC power control. A 1-bit value to reduce the power consumption of the voice ADC. If bit VAP = 1, then the state is power-on; if bit VAP = 0 (default), then the state is power-off. DSD mode selection. A 1-bit value to select the DSD mode. If bit DSD = 1, then the DSD mode; if bit DSD = 0 (default), then the normal mode. System clock frequency. A 2-bit value to select the used external clock frequency. 128fs system clock for the DAC can be used by setting bit DVD = 1. Default 00. See Table 22. Operating mode selection. A 2-bit value to select the operation mode of the audio ADC and DAC. Default 00. See Table 23. Sampling frequency. A 2-bit value to select the sampling frequency of the audio ADC and DAC in the WS mode. Default 01. See Table 24. ADC clock enable. A 1-bit value to enable the audio ADC clock. If bit ACE = 1 (default), then the clock is enabled; if bit ACE = 0, then the clock is disabled. ADC power control. A 1-bit value to reduce the power consumption of the audio ADC. If bit ADP = 1, then the state is power-on; if bit ADP = 0 (default), then the state is power-off. DAC clock enable. A 1-bit value to enable the DAC clock. If bit DCE = 1 (default), then the clock is enabled; if bit DCE = 0, then the clock is disabled. DAC power control. A 1-bit value to reduce the power consumption of the DAC. If bit DAP = 1, then the state is power-on; if bit DAP = 0 (default), then the state is power-off.
10 9 to 8 7 to 6 5 to 4 3 2
DSD SC[1:0] OP[1:0] FS[1:0] ACE ADP
1 0
DCE DAP
2002 Nov 21
26
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 21 Voice ADC sampling frequency bits VFS1 0 0 1 1 VFS0 0 1 0 1 FUNCTION 6.25 to 12.5 kHz (default) 12.5 to 25 kHz 25 to 50 kHz reserved
UDA1338H
Table 22 System clock frequency bits DAC SC1 0 0 1 1 SC0 0 1 0 1 ADC BIT DVD = 0 256fs 384fs 512fs 768fs 256fs 384fs 512fs 768fs BIT DVD = 1 128fs 192fs 256fs 384fs default REMARK
Table 23 Operating mode bits OP1 0 0 1 1 OP0 0 1 0 1 ADC MODE SYSCLK (256fs, 384fs, 512fs or 768fs) SYSCLK (256fs, 384fs, 512fs or 768fs) WSAD (1fs) WSDA (1fs) DAC MODE SYSCLK (128fs, 256fs, 384fs, 512fs or 768fs) WSDA (1fs) SYSCLK (128fs, 256fs, 384fs, 512fs or 768fs) WSDA (1fs) REMARK default
Table 24 Audio ADC and DAC sampling frequency bits FS1 0 0 1 1 11.4 FS0 0 1 0 1 FUNCTION 12.5 to 25 kHz 25 to 50 kHz (default) 50 to 100 kHz 100 to 200 kHz
Audio ADC and DAC subsystem settings
Table 25 Audio ADC and DAC subsystem register (address 01H) BIT Symbol Reset default BIT Symbol Reset default 15 DC 1 7 DAG 0 14 PAB 0 6 FIL 0 13 PAA 0 5 DVD 0 12 MTB 0 4 DIS1 0 11 MTA 0 3 DIS0 0 10 AIF2 0 2 DIF2 0 9 AIF1 0 1 DIF1 0 8 AIF0 0 0 DIF0 0
2002 Nov 21
27
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 26 Description of the audio ADC and DAC subsystem register bits BIT 15 14 13 12 11 10 to 8 7 6 5 SYMBOL DC PAB PAA MTB MTA AIF[2:0] DAG FIL DVD DESCRIPTION
UDA1338H
ADC DC-filter. A 1-bit value to enable the digital DC-filter of the ADC. If bit DC = 1 (default), then the DC-filtering is active; if bit DC = 0, then there is no DC-filtering. Polarity ADC 2 control. A 1-bit value to control the ADC 2 polarity. If bit PAB = 1, then the polarity is inverted; if bit PAB = 0 (default), then the polarity is non-inverted. Polarity ADC 1 control. A 1-bit value to control the ADC 1 polarity. If bit PAA = 1, then the polarity is inverted; if bit PAA = 0 (default), then the polarity is non-inverted. Mute ADC 2. A 1-bit value to enable the digital mute of ADC 2. If bit MTB = 1, then ADC 2 is soft muted; if bit MTB = 0 (default), then ADC 2 is not muted. Mute ADC 1. A 1-bit value to enable the digital mute of ADC 1. If bit MTA = 1, then ADC 1 is soft muted; if bit MTA = 0 (default), then ADC 1 is not muted. ADC output data interface format. A 3-bit value to select the used data format to the I2S-bus ADC output interface. Default 000. See Table 27. DAC gain switch. A 1-bit value to select the DAC gain. If bit DAG = 1, then the gain is 6 dB; if bit DAG = 0 (default), then the gain is 0 dB. Filter selection. A 1-bit value to select the interpolation filter characteristics. If bit FIL = 1, then slow roll-off; if bit FIL = 0 (default), then sharp roll-off. 192 kHz sampling mode selection. A 1-bit value to select the oversampling rate of the noise shaper. The 64fs rate is used for 192 and 176.4 kHz sampling frequencies. If 7bit DVD = 1, then 64fs rate is selected (192 kHz sampling mode); if bit DVD = 0 (default), then 128fs rate is selected. Data interface selection. A 2-bit value to select the data interface connection. Default 00. See Table 28. DAC input data interface format. A 3-bit value to select the used data format to the I2S-bus DAC input interface. Default 000. See Table 27.
4 to 3 2 to 0
DIS[1:0] DIF[2:0]
Table 27 Data interface format bits AIF2 DIF2 0 0 0 0 1 1 1 1 AIF1 DIF1 0 0 1 1 0 0 1 1 AIF0 FUNCTION DIF0 0 1 0 1 0 1 0 1 I2S-bus format (default) LSB-justified format, 16 bits LSB-justified format, 20 bits LSB-justified format, 24 bits MSB-justified format multichannel format, 20 bits multichannel format, 24 bits (format 1) multichannel format, 24 bits (format 2)
2002 Nov 21
28
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 28 Data interface selection bits DIS1 0 0 1 1 11.5 DIS0 0 1 0 1 INPUT TO DAC
UDA1338H
DATADA1 to DAC channel 1 and 2, DATADA2 to DAC channel 3 and 4, and DATADA3 to DAC channel 5 and 6 (default) DATADA1 to DAC channels 1 to 6 DATADA2 to DAC channels 1 to 6 DATADA3 to DAC channels 1 to 6
Voice ADC system settings
Table 29 Voice ADC system register (address 02H) BIT Symbol Reset default BIT Symbol Reset default 15 - 0 7 BCK1 0 14 - 0 6 BCK0 1 13 - 0 5 WSM 1 12 - 0 4 VH1 0 11 - 0 3 VH0 1 10 - 0 2 PVA 0 9 - 0 1 MTV 0 8 - 0 0 VIF 0
Table 30 Description of the voice ADC system register bits BIT 15 to 8 7 to 6 5 4 to 3 2 SYMBOL - BCK[1:0] WSM VH[1:0] PVA default 0000 0000 BCK frequency of voice ADC. A 2-bit value to select the BCK frequency of the voice ADC in the WSV-out mode. Default 01. See Table 31. WSV mode selection. A 1-bit value to select the WSV mode of the voice ADC. If bit WSM = 1 (default), then WSV-in mode; if bit WSM = 0, then WSV-out mode. Voice ADC high-pass filter setting. A 2-bit value to enable the high-pass filter of the voice ADC. Default 01. See Table 32. Polarity voice ADC control. A 1-bit value to control the voice ADC polarity. If bit PVA = 1, then the polarity is inverted; if bit PVA = 0 (default), then the polarity is non-inverted. Mute voice ADC. A 1-bit value to enable the digital mute of the voice ADC. If bit MTV = 1, then the voice ADC is soft muted; if bit MTV = 0 (default), then the voice ADC is not muted. Voice ADC interface format. A 1-bit value to select the data interface format of the voice ADC. If bit VIF = 1, then mono-channel format; if bit VIF = 0 (default), then I2S-bus format. DESCRIPTION
1
MTV
0
VIF
Table 31 BCK frequency of voice ADC bits BCK1 0 0 1 1 BCK0 0 1 0 1 FUNCTION 32fs 64fs (default) 128fs 256fs 29
2002 Nov 21
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 32 Voice ADC high-pass filter setting bits VH1 0 0 1 1 11.6 VH0 0 1 0 1 high-pass filter off fc = 0.00008fs (default) fc = 0.0125fs fc = 0.025fs FUNCTION
UDA1338H
Status output register (read only)
Table 33 Status output register (address 0FH) BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 VS 12 - 4 AS1 11 - 3 AS0 10 - 2 DS2 9 - 1 DS1 8 - 0 DS0
Table 34 Description of status output register bits. BIT 15 to 6 5 SYMBOL - VS not used Voice ADC status. A 1-bit value to indicate the hard mute status of the voice ADC. If bit VS = 1, then power-down is ready and the clock may be disabled; if bit VS = 0, then power-down is not ready and the clock should not be disabled. ADC 2 status. A 1-bit value to indicate the hard mute status of ADC 2. If bit AS1 = 1, then power-down is ready and the clock may be disabled; if bit AS1 = 0, then power-down is not ready and the clock should not be disabled. ADC 1 status. A 1-bit value to indicate the hard mute status of ADC 1. If bit AS0 = 1, then power-down is ready and the clock may be disabled; if bit AS0 = 0, then power-down is not ready and the clock should not be disabled. DAC channel 5 and 6 status. A 1-bit value to indicate the hard mute status of DAC channel 5 and 6. If bit DS2 = 1, then power-down is ready and the clock may be disabled; if bit DS2 = 0, then power-down is not ready and the clock should not be disabled. DAC channel 3 and 4 status. A 1-bit value to indicate the hard mute status of DAC channel 3 and 4. If bit DS1= 1, then power-down is ready and the clock may be disabled; if bit DS1 = 0, then power-down is not ready and the clock should not be disabled. DAC channel 1 and 2 status. A 1-bit value to indicate the hard mute status of DAC channel 1 and 2. If bit DS0 = 1, then power-down is ready and the clock may be disabled; if bit DS0 = 0, then power-down is not ready and the clock should not be disabled. DESCRIPTION
4
AS1
3
AS0
2
DS2
1
DS1
0
DS0
2002 Nov 21
30
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
11.7 DAC channel selection
UDA1338H
Table 35 DAC channel select register (address 10H) BIT Symbol Reset default BIT Symbol Reset default 15 MIX1 0 7 SEL1 0 14 MIX0 0 6 SEL0 0 13 MC5 0 5 CS5 0 12 MC4 0 4 CS4 0 11 MC3 0 3 CS3 0 10 MC2 0 2 CS2 0 9 MC1 0 1 CS1 0 8 MC0 0 0 CS0 0
Table 36 Description of DAC channel select register bits BIT 15 to 14 13 to 8 SYMBOL MIX[1:0] MC[5:0] DESCRIPTION DAC mixer setting. A 2-bit value to enable the DAC mixer. Default 00. See Table 37. DAC mixing channel selection. A group of 6 enable bits to make DAC mixing channels ready for receiving feature settings through register address 11H. Only selected registers accept new settings. Default 00 0000 (no channel ready). See Table 38. Feature selection. A 2-bit value to select the features to be set through register address 11H. When the feature settings are written, only selected feature settings are changed and non selected features are kept unchanged. Default 00. See Table 39. DAC channel selection. A group of 6 enable bits to make DAC channel ready for receiving feature settings through register address 11H. Default 00 0000 (no channel ready). See Table 38.
7 and 6
SEL[1:0]
5 to 0
CS[5:0]
Table 37 DAC mixer setting bits MIX1 0 0 1 1 MIX0 0 1 0 1 no mixing (default) no mixing mixing ADC 1 mixing ADC 2 FUNCTION
Table 38 DAC channel and mixing channel selection bits MC5 CS5 0 : 0 : 1 MC4 CS4 0 : 0 : 1 MC3 CS3 0 : 1 : 1 MC2 CS2 0 : 0 : 1 MC1 CS1 0 : 1 : 1 MC0 FUNCTION CS0 1 : 0 : 1 all channels selected channel 2 and channel 4 selected channel 1 selected
2002 Nov 21
31
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 39 Feature selection bits SEL1 0 0 1 1 11.8 SEL0 0 1 0 1 all features (default) volume mute and quick mute de-emphasis, polarity and input channel selection FUNCTION
UDA1338H
DAC features settings
Table 40 DAC features register (addresses 11H) BIT Symbol Reset default BIT Symbol Reset default 15 ICS1 0 7 VC7 0 14 ICS0 0 6 VC6 0 13 DE2 0 5 VC5 0 12 DE1 0 4 VC4 0 11 DE0 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
Table 41 Description of DAC features register bits BIT 15 to 14 SYMBOL ICS[1:0] DESCRIPTION Input channel selection. A 2-bit value to select the input channels. As the controlled channels are paired off, this 2-bit value must be written to each odd channel register. Default 00. See Table 42. De-emphasis setting. A 3-bit value to enable the digital de-emphasis filter. Default 000. See Table 43. Polarity DAC control. A 1-bit value to control the DAC polarity. If bit PD = 1, then the polarity is inverted; if bit PD = 0 (default), then the polarity is non-inverted. Muting. A 1-bit value to enable the digital mute. All the DAC outputs are muted at start-up. It is necessary to explicitly switch off for the audio output by means of bit MT. If bit MT = 1 (start-up), then muting; if bit MT = 0 (default), then no muting. Quick mute. A 1-bit value to set the quick mute mode. If bit QM = 1 (start-up), then quick mute mode; if bit QM = 0 (default), then soft mute mode. Interpolator volume control. An 8-bit value to program the volume attenuation of each channel. The range is from 0 to -53 dB in steps of 0.25 dB, from -53 to -80 dB in steps of 3 dB and - dB. Default 0000 0000. See Table 44.
13 to 11 10 9
DE[2:0] PD MT
8 7 to 0
QM VC[7:0]
Table 42 Input channel selection bits ICS1 0 0 1 1 ICS0 0 1 0 1 INPUT TO DAC OUTPUT left channel input data to odd channel output; right channel input data to even channel output left channel input data to odd and even channel outputs right channel input data to odd and even channel outputs left channel input data to even channel output; right channel input data to odd channel output
2002 Nov 21
32
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 43 De-emphasis bits DE2 0 0 0 0 1 1 1 1 DE1 0 0 1 1 0 0 1 1 DE0 0 1 0 1 0 1 0 1 no de-emphasis (default) de-emphasis of 32 kHz de-emphasis of 44.1 kHz de-emphasis of 48 kHz de-emphasis of 96 kHz not used not used not used FUNCTION
UDA1338H
Table 44 Interpolator volume control bits VC7 0 0 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 : 1 VC6 0 0 0 0 0 0 : 1 1 1 1 1 1 1 1 1 1 1 : 1 VC5 0 0 0 0 0 0 : 0 0 0 1 1 1 1 1 1 1 1 : 1 VC4 0 0 0 0 0 0 : 1 1 1 0 0 0 0 1 1 1 1 : 1 VC3 0 0 0 0 0 0 : 0 1 1 0 0 1 1 0 0 1 1 : 1 VC2 0 0 0 0 1 1 : 1 0 1 0 1 0 1 0 1 0 1 : 1 VC1 0 0 1 1 0 0 : 0 0 0 0 0 0 0 0 0 0 0 : 1 VC0 0 1 0 1 0 1 : 0 0 0 0 0 0 0 0 0 0 0 : 1 VOLUME (dB) 0 (default) -0.25 -0.50 -0.75 -1.00 -1.25 : -53 -56 -59 -62 -65 -68 -71 -74 -77 -80 - : -
2002 Nov 21
33
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
11.9 DAC channel 1 to 6 settings
UDA1338H
All the DAC features which are written in register 11H are copied into the odd channel registers. Table 45 DAC channel 1, 3 and 5 registers (addresses 12H, 14H and 16H) BIT Symbol Reset default BIT Symbol Reset default 15 ICS1 0 7 VC7 0 14 ICS0 0 6 VC6 0 13 DE2 0 5 VC5 0 12 DE1 0 4 VC4 0 11 DE0 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
All the DAC features which are written in register 11H are copied into the even channel registers, except the bits ICS[1:0]. Table 46 DAC channel 2, 4 and 6 registers (addresses 13H, 15H and 17H) BIT Symbol Reset default BIT Symbol Reset default 15 - 0 7 VC7 0 14 - 0 6 VC6 0 13 DE2 0 5 VC5 0 12 DE1 0 4 VC4 0 11 DE0 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
11.10 DAC mixing channel settings All the DAC features which are written in register 11H are copied into the odd mixing channel registers, except the bits DE[2:0]. Table 47 DAC mixing channel 1, 3 and 5 registers (addresses 18H, 1AH and 1CH) BIT Symbol Reset default BIT Symbol Reset default 15 ICS1 0 7 VC7 0 14 ICS0 0 6 VC6 0 13 - 0 5 VC5 0 12 - 0 4 VC4 0 11 - 0 3 VC3 0 10 PD 0 2 VC2 0 9 MT 0 1 VC1 0 8 QM 0 0 VC0 0
All the DAC features which are written in register 11H are copied into the even channel registers, except the bits ICS[1:0] and DE[2:0].
2002 Nov 21
34
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 48 DAC mixing channel 2, 4 and 6 registers (addresses 19H, 1BH and 1DH) BIT Symbol Reset default BIT Symbol Reset default 15 - 0 7 VC7 0 14 - 0 6 VC6 0 13 - 0 5 VC5 0 12 - 0 4 VC4 0 11 - 0 3 VC3 0 10 PD 0 2 VC2 0
UDA1338H
9 MT 0 1 VC1 0
8 QM 0 0 VC0 0
11.11 Audio ADC 1 and ADC 2 input amplifier gain settings Table 49 Audio ADC input amplifier gain register (address 20H) BIT Symbol Reset default BIT Symbol Reset default 15 - 0 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 IB3 0 3 IA3 0 10 IB2 0 2 IA2 0 9 IB1 0 1 IA1 0 8 IB0 0 0 IA0 0
Table 50 Description of audio ADC input amplifier gain register bits BIT 15 to 12 11 to 8 7 to 4 3 to 0 SYMBOL - IB[3:0] - IA[3:0] default 0000 Audio ADC 2 input amplifier gain. A 4-bit value to program the input amplifier gain in steps of 3 dB (9 settings). Default 0000. See Table 51. default 0000 Audio ADC 1 input amplifier gain. A 4-bit value to program the input amplifier gain in steps of 3 dB (9 settings). Default 0000. See Table 51. DESCRIPTION
Table 51 Audio ADC input amplifier gain bits IA3 IB3 0 0 0 0 0 0 0 0 1 IA2 IB2 0 0 0 0 1 1 1 1 0 IA1 IB1 0 0 1 1 0 0 1 1 0 IA0 GAIN (dB) IB0 0 1 0 1 0 1 0 1 0 0 (default) +3 +6 +9 +12 +15 +18 +21 +24
2002 Nov 21
35
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
11.12 Voice ADC gain settings Table 52 Voice ADC input amplifier gain register (address 21H) BIT Symbol Reset default BIT Symbol Reset default 15 - - 7 - 0 14 - - 6 - 0 13 - - 5 - 0 12 - - 4 IV4 0 11 - - 3 IV3 0 10 - - 2 IV2 0
UDA1338H
9 - - 1 IV1 0
8 - - 0 IV0 0
Table 53 Description of voice ADC input amplifier gain register bits BIT 15 to 8 7 to 5 4 to 0 SYMBOL - - IV[4:0] not used default 000 Voice ADC input amplifier gain. A 5-bit value to program the voice amplifier gain in steps of 1.5 dB (21 settings). Default 0 0000. See Table 54. DESCRIPTION
Table 54 Voice ADC input amplifier gain bits IV4 0 0 0 0 0 0 : 1 1 : 1 IV3 0 0 0 0 0 0 : 0 0 : 1 IV2 0 0 0 0 1 1 : 0 1 : 1 IV1 0 0 1 1 0 0 : 1 0 : 1 IV0 0 1 0 1 0 1 : 1 0 : 1 GAIN (dB) 0 (default) +1.5 +3 +4.5 +6 +7.5 : +28.5 +30 not used not used
11.13 Supplemental settings 1 Table 55 Supplemental settings 1 register (address 30H) BIT Symbol Reset default BIT Symbol Reset default 15 - 0 7 PDT 0 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 - 0 3 - 0 10 - 0 2 - 0 9 - 0 1 - 0 8 - 0 0 - 0
2002 Nov 21
36
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Table 56 Description of supplemental settings 1 register bits BIT 15 to 8 7 6 to 0 SYMBOL - PDT - default 0000 0000 DESCRIPTION
UDA1338H
Power down time. A 1-bit value to select the time of the SDAC power-down sequence. If bit PDT = 1, then 1024/fs seconds; if bit PDT = 0 (default), then 512/fs seconds. default 000 0000
11.14 Supplemental settings 2 Table 57 Supplemental settings 2 register (address 31H) BIT Symbol Reset default BIT Symbol Reset default 15 - 0 7 - 0 14 - 0 6 DITH2 0 13 - 0 5 DITH1 0 12 - 0 4 DITH0 0 11 - 0 3 - 0 10 - 0 2 - 0 9 - 0 1 VMTP 0 8 - 0 0 PDLNA 0
Table 58 Description of supplemental settings 2 register bits BIT 15 to 7 6 to 4 3 to 2 1 SYMBOL - DITH[2:0] - VMTP default 0000 0000 0 DAC dither control. A 3-bit value to control the dithering of the SDAC. Default 000. See Table 59. default 00 Voice mute period control. A 1-bit value to select the voice ADC mute period at power-up. If bit VMTP = 1, then mute for 1024 samples (1024/fs); if bit VMTP = 0 (default), then mute for 2048 samples (2048/fs). Power-down voice LNA. A 1-bit value to power-down the voice ADC LNA. It should be noted that disabling the LNA requires a recovery time defined by the external RC circuit. If bit PDNLA = 1, then power-down; if bit PDNLA = 0 (default), then power-on. DESCRIPTION
0
PDLNA
Table 59 DAC dither control bits DITH2 0 0 0 0 1 1 1 1 DITH1 0 0 1 1 0 0 1 1 DITH0 0 1 0 1 0 1 0 1 DC dither (mid level); default reserved reserved reserved DC dither (low level) DC plus AC dither (low level) DC dither (high level) DC plus AC dither (high level) FUNCTION
2002 Nov 21
37
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal(max) Tstg Tamb Vesd PARAMETER supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic discharge voltage note 2 note 3 Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor. 13 HANDLING note 1 CONDITIONS - - -65 -20 -2000 -200 MIN.
UDA1338H
MAX. 4.0 150 +125 +85 +2000 +200 V
UNIT C C C V V
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 14 QUALITY SPECIFICATION In accordance with the "General specification for integrated circuits (SNW-FQ-611D)". 15 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 85 UNIT K/W
2002 Nov 21
38
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
16 DC CHARACTERISTICS VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; Tamb = 25 C; RL = 22 k; all voltages referenced to ground (pins VSS); unless otherwise specified. SYMBOL Supplies VDDA(AD) VDDA(DA) VDDD IDDA(AD) IDDA(DA) IDDD ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current DAC analog supply current digital supply current note 1 note 1 note 1 fADC = 48 kHz fADC = 96 kHz fDAC = 48 kHz fDAC = 96 kHz fADC = fDAC = 48 kHz; fVOICE = 48 kHz fADC = fDAC = 96 kHz; fVOICE = 48 kHz audio and voice ADCs power-down DAC power-down 2.7 2.7 2.7 - - - - - - - - 2.0 - - - IOH = -2 mA IOL = 2 mA 0.85VDDD - 3.3 3.3 3.3 30 31 20 32 31 55 tbf tbf - - - - - - 3.6 3.6 3.6 - - - - - - - - - 0.8 1 10 - 0.4 V V V mA mA mA mA mA mA mA mA V V A pF V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDDD(pd)
digital supply current in Power down-mode
Digital input pins (5 V tolerant TTL compatible) VIH VIL ILI Ci VOH VOL Vref VADCP VADCN Ro Ri(ADC) Ri(VADC) HIGH-level input voltage LOW-level input voltage input leakage current input capacitance HIGH-level output voltage LOW-level output voltage
Digital output pins
Analog-to-digital converter reference voltage on pin with respect to Vref VSSA(AD) positive reference voltage of ADC negative reference voltage of ADC output resistance on pin Vref input resistance of audio ADC input resistance of voice ADC load resistance output resistance 0.45VDDA(AD) 0.5VDDA(AD) - 0.0 - - - VDDA(AD) 0.0 5 10 5 0.55VDDA(AD) V - 0.0 - - - V V k k k
Digital-to-analog converter RL Ro Note 1. All supply connections must be made to the same power supply unit. 4 - - 1 - - k k
2002 Nov 21
39
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
17 AC CHARACTERISTICS VDDD = VDDA(AD) = VDDA(DA) = 3.3 V; fi = 1 kHz; Tamb = 25 C; RL = 22 k; sampling frequency fs = 48 kHz; all voltages referenced to ground (pins VSS); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. -2.5 - - - - - - - - - TYP. -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 -1.2 0.1 MAX. -0.7 - - - - - - - - - UNIT
Audio analog-to-digital converter D0 digital output level at 0 dB setting; 900 mV input; notes 1 and 2 at 3 dB setting; 637 mV input; note 2 at 6 dB setting; 451 mV input; note 2 at 9 dB setting; 319 mV input; note 2 at 12 dB setting; 226 mV input; note 2 at 15 dB setting; 160 mV input; note 2 at 18 dB setting; 113 mV input; note 2 at 21 dB setting; 80 mV input; note 2 at 24 dB setting; 57 mV input; note 2 Vi input voltage unbalance between channels dB dB dB dB dB dB dB dB dB dB
2002 Nov 21
40
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
SYMBOL (THD + N)/S
PARAMETER
CONDITIONS - - - - - - - - - - - - - - - - - -
MIN.
TYP. -90 -90 -90 -90 -90 -89 -87 -85 -83 -75 tbf tbf tbf tbf tbf tbf tbf tbf
MAX. -83 - - - - - - - - - - - - - - - - -
UNIT dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
total harmonic normal mode; at -1 dBFS distortion-plus-noise to signal ratio at 0 dB setting at 3 dB setting at 6 dB setting at 9 dB setting at 12 dB setting at 15 dB setting at 18 dB setting at 21 dB setting at 24 dB setting normal mode; at -20 dBFS at 0 dB setting at 3 dB setting at 6 dB setting at 9 dB setting at 12 dB setting at 15 dB setting at 18 dB setting at 21 dB setting at 24 dB setting normal mode; at -60 dBFS; A-weighted at 0 dB setting at 3 dB setting at 6 dB setting at 9 dB setting at 12 dB setting at 15 dB setting at 18 dB setting at 21 dB setting at 24 dB setting
- - - - - - - - - 94 - -
-40 -40 -40 -39 -38 -37 -35 -32 -30 100 100 tbf
-34 - - - - - - - - - - -
dB dB dB dB dB dB dB dB dB dB dB dB
S/N cs PSRR
signal-to-noise ratio channel separation power supply rejection ratio
code = 0; A-weighted fripple = 1 kHz; Vripple = 30 mV (p-p)
2002 Nov 21
41
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
SYMBOL
PARAMETER
CONDITIONS - - - - - -
MIN.
TYP.
MAX. - - - - - -
UNIT
Voice analog-to-digital converter Vi(rms) (THD + N)/S input voltage (RMS value) at 0 dBFS digital output; 2.2 k source impedance 50.0 -78 -65 -47 87 tbf mV dB dB dB dB dB
total harmonic at -1 dBFS distortion-plus-noise to signal ratio at -20 dBFS at -40 dBFS; A-weighted signal-to-noise ratio power supply rejection ratio code = 0; A-weighted fripple = 1 kHz; Vripple = 30 mV (p-p)
S/N PSRR
Digital-to-analog converter DIFFERENTIAL MODE Vo(rms) Vo (THD + N)/S output voltage (RMS value) output voltage unbalance between channels total harmonic at 0 dBFS distortion-plus-noise to signal ratio at -20 dBFS at -60 dBFS; A-weighted S/N cs PSRR signal-to-noise ratio channel separation power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) at 0 dBFS digital input code = 0; A-weighted at 0 dBFS digital input 1.9 - - - - 107 - - 2.0 <0.1 -100 -90 -50 114 117 tbf 2.1 - -93 - -45 - - - V dB dB dB dB dB dB dB
SINGLE-ENDED MODE Vo(rms) Vo (THD + N)/S output voltage (RMS value) output voltage unbalance between channels total harmonic at 0 dBFS distortion-plus-noise to signal ratio at -20 dBFS at -60 dBFS; A-weighted S/N cs PSRR Notes 1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. signal-to-noise ratio channel separation power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) code = 0; A-weighted - - - - - - - - 1.0 <0.1 -90 -85 -45 110 114 tbf - - - - - - - - V dB dB dB dB dB dB dB
2002 Nov 21
42
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
18 TIMING VDDD = VDDA(AD) = VDDA(AD) = 2.7 to 3.6 V; Tamb = -20 to +85 C; typical timing specified at sampling frequency fs = 48 kHz; unless otherwise specified. SYMBOL System clock (see Fig.16) Tsys system clock cycle time note 1 fsys = 256fs fsys = 384fs fsys = 512fs fsys = 768fs tCWL tCWH system clock LOW time system clock HIGH time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz I2S-bus interface SERIAL DATA OF AUDIO ADC AND DAC (see Fig.17) fBCK Tcy(BCK) tBCKH tBCKL tr tf tsu(WS) th(WS) tsu(DATAI) th(DATAI) th(DATAO) td(DATAO-BCK) td(DATAO-WS) fBCKV Tcy(BCKV) tBCKVH tBCKVL tr tf tsu(WSV) th(WSV) th(DATAV) td(DATAV-BCKV) td(DATAV-WSV) 2002 Nov 21 audio bit clock frequency BCK cycle time bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data input set-up time data input hold time data output hold time data output to bit clock delay data output to word select delay note 2 - - 30 30 - - 10 10 10 10 0 - - note 2 - - 50 50 - - 10 10 0 - - 43 - - - - - - - - - - - - - - - - - - - - - - - - 12.8 78 - - 20 20 - - - - - 30 30 MHz ns ns ns ns ns ns ns ns ns ns ns ns 35 23 17 17 0.3Tsys 0.4Tsys 0.3Tsys 0.4Tsys 81 54 41 27 - - - - 780 520 390 260 0.7Tsys 0.6Tsys 0.7Tsys 0.6Tsys ns ns ns ns ns ns ns ns PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
SERIAL DATA OF VOICE ADC voice bit clock frequency BCKV cycle time bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data output hold time data output to bit clock delay data output to word select delay 6.4 156 - - 20 20 - - - 30 30 MHz ns ns ns ns ns ns ns ns ns ns
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
SYMBOL td(WSV-BCKV)
PARAMETER word select to bit clock delay
CONDITIONS WSV-out mode
MIN. -30 -
TYP.
MAX. +30
UNIT ns
L3-bus interface (see Figs 18 and 19) L3CLOCK TIMING fcy(CLK)L3 Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D tstp(L3) L3DATA TIMING tsu(L3)DA th(L3)DA td(L3)R tdis(L3)R I2C-bus L3DATA set-up time in data transfer and address mode L3DATA hold time in data transfer and address mode L3DATA delay time for read data L3DATA disable time for read data interface timing (see Fig.20) - - - 190 30 0 0 - - - - - - 50 50 ns ns ns ns L3CLK frequency L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time - 500 250 250 - - - - - - - - - 2000 - - - - - - - - kHz ns ns ns
L3MODE TIMING L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode L3MODE stop time in data transfer mode 190 190 190 190 190 ns ns ns ns ns
SCL TIMING fSCL tLOW tHIGH tr tf SDA TIMING tBUF tSU;STA tHD;STA tSU;DAT tHD;DAT tSU;STO tSP Cb bus free time between STOP and START condition set-up time repeated START hold time START condition data set-up time data hold time set-up time STOP condition pulse width of spikes capacitive load for each bus line note 4 1.3 0.6 0.6 100 0 0.6 0 - - - - - - - - - - - - - - - 50 400 s s s ns s s ns pF SCL clock frequency SCL LOW time SCL HIGH time rise time SDA and SCL fall time SDA and SCL note 3 note 3 0 1.3 0.6 400 - - 300 300 kHz s s ns ns
20 + 0.1Cb - 20 + 0.1Cb -
2002 Nov 21
44
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
Notes 1. The system clock should not exceed 58 MHz in any mode. 2. The bit clock frequency should not exceed 256 times the corresponding sampling frequency. 3. Cb is the total capacitance for each bus line. 4. To be suppressed by the input filter.
UDA1338H
handbook, full pagewidth
t CWH
t CWL Tsys
MGR984
Fig.16 System clock timing.
handbook, full pagewidth
WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK)
tr
tf
t d(DATAO-WS)
t h(DATAO)
t su(DATAI) t h(DATAI) DATAI
MGS756
Fig.17 I2S-bus serial interface timing.
2002 Nov 21
45
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
handbook, full pagewidth
L3MODE th(L3)A tCLK(L3)L tsu(L3)A L3CLOCK tCLK(L3)H th(L3)A tsu(L3)A
Tcy(CLK)(L3) tsu(L3)DA th(L3)DA
L3DATA
BIT 0
BIT 7
MGL723
Fig.18 L3-bus address mode timing.
handbook, full pagewidth
tstp(L3)
L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D
L3CLOCK tsu(L3)DA th(L3)DA L3DATA write BIT 0 BIT 7
L3DATA read td(L3)R tdis(L3)R
MGU015
Fig.19 L3-bus data transfer (write and read) mode timing.
2002 Nov 21
46
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
UDA1338H
handbook, full pagewidth
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA tSU;STA tSU;STO
S
tHD;DAT
tHIGH
Sr
P
S
MSC610
Fig.20 I2C-bus timing
2002 Nov 21
47
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
19 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
UDA1338H
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
2002 Nov 21
48
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
20 SOLDERING 20.1 Introduction to soldering surface mount packages
UDA1338H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 20.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 20.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Nov 21
49
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
20.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
UDA1338H
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Nov 21
50
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
21 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
UDA1338H
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 22 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 23 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Nov 21
51
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
24 PURCHASE OF PHILIPS I2C COMPONENTS
UDA1338H
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Nov 21
52
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
NOTES
UDA1338H
2002 Nov 21
53
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
NOTES
UDA1338H
2002 Nov 21
54
Philips Semiconductors
Preliminary specification
Multichannel audio coder-decoder
NOTES
UDA1338H
2002 Nov 21
55
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/2/pp56
Date of release: 2002
Nov 21
Document order number:
9397 750 10089

▲Up To Search▲

Price & Availability of UDA1338H

	To Download UDA1338H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .